AMD Athlon™ Processor Key Architectural Features 

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The AMD64 core provides leading-edge performance for both 32-bit and 64-bit applications

• AMD64 technology provides full-speed support for x86 code base without compromising performance
• 40-bit physical addresses, 48-bit virtual addresses
• Sixteen 64-bit integer registers
• Sixteen 128-bit SSE/SSE2/SSE3 registers
• AMD Digital Media XPress™ provides support for SSE, SSE2, SSE3 and MMX instructions

A high-bandwidth, low-latency integrated DDR memory controller

• Supports PC-3200 (DDR-400), PC-2700 (DDR-333), PC-2100 (DDR-266) or PC-1600 (DDR-1600) SDRAM unbuffered DIMMs (socket 939); supports PC2-5300 (DDR2-667), PC2-4200 (DDR2-533) or PC2-3200 (DDR2-400) SDRAM unbuffered DIMMs (socket AM2)
• Support for 64-bit DDR (socket 939) or DDR2 (socket AM2) SDRAM memory
• Up to 6.4GB/s (socket 939) or 10.6GB/s (socket AM2) memory bandwidth

HyperTransport™ Technology for high speed I/O communication

• One 16-bit link up to 2000MHz bidirectional
• Up to 8GB/s HyperTransport™ I/O bandwidth
• Up to 14.4GB/s (socket 939) or 18.6GB/s (socket AM2) total delivered processor-to-system bandwidth (HyperTransport bus + memory bus)

Large high performance on-chip cache

• 64KB Level 1 instruction cache
• 64KB Level 1 data cache
• Up to 1MB (socket 939) or 512KB (socket AM2) Level 2 cache

*As part of a comprehensive security program, AMD strongly recommends enabling Enhanced Virus Protection (EVP) and using up to date third party anti-virus softwarve.

© 2009 Advanced Micro Devices, Inc. AMD, the AMD Arrow logo, AMD Athlon, 3DNow!, AMD Digital Media Xpress, Cool'n'Quiet, and combinations thereof, are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Linux is a registered trademark of Linus Torvalds. Microsoft and Windows are registered trademarks of Microsoft Corporation in the U.S. and/or other jurisdictions. Other names are for informational purposes only and may be trademarks of their respective owners.